Residual Vulnerabilities to Power side channel attacks of lightweight ciphers cryptography competition Finalists

The protection of communications between Internet of Things (IoT) devices is of great concern because the information exchanged contains vital sensitive data. Malicious agents seek to exploit those data to extract secret information about the owners or the system. Power side channel attacks are of great concern on these devices because their power consumption unintentionally leaks information correlatable to the device\u27s secret data. Several studies have demonstrated the effectiveness of authenticated encryption with advanced data, in protecting communications with these devices. A comprehensive evaluation of the seven (out of 10) algorithm finalists of the National Institute of Standards and Technology (NIST) IoT lightweight cipher competition that do not integrate built‐in countermeasures is proposed. The study shows that, nonetheless, they still present some residual vulnerabilities to power side channel attacks (SCA). For five ciphers, an attack methodology as well as the leakage function needed to perform correlation power analysis (CPA) is proposed. The authors assert that Ascon, Sparkle, and PHOTON‐Beetle security vulnerability can generally be assessed with the security assumptions “Chosen ciphertext attack and leakage in encryption only, with nonce‐misuse resilience adversary (CCAmL1)” and “Chosen ciphertext attack and leakage in encryption only with nonce‐respecting adversary (CCAL1)”, respectively. However, the security vulnerability of GIFT‐COFB, Grain, Romulus, and TinyJambu can be evaluated more straightforwardly with publicly available leakage models and solvers. They can also be assessed simply by increasing the number of traces collected to launch the attack

Product Specification: Distributed Trust Model System (DOE-PSU-0000922-4)

A Distributed Trust Model (DTM) System is a supervisory component within an energy grid of things. The role of a DTM System is to implement the trust aspects of an energy services interface. The DTM System augments existing security measures by monitoring the communication between the various EGoT System actors and quantifying metrics of trust of each actor

Trust Model System for the Energy Grid of Things Network Communications

Network communication is crucial in the Energy Grid of Things (EGoT). Without a network connection, the energy grid becomes just a power grid where the energy resources are available to the customer uni-directionally. A mechanism to analyze and optimize the energy usage of the grid can only happen through a medium, a communications network, that enables information exchange between the grid participants and the service provider. Security implementers of EGoT network communication take extraordinary measures to ensure the safety of the energy grid, a critical infrastructure, as well as the safety and privacy of the grid participants. With the dynamic nature of network communication of the EGoT, the information provided by the customer or the service provider can be falsified by a malicious attacker. Therefore, a trust model is necessary to monitor any abnormal activities. This paper describes a distributed trust model system that meets the need of the EGoT. This paper describes methods for evaluating and improving the distributed trust model using standard hypothesis testing metrics such as true positive, false positive, true negative, false negative, equal error rate, and F1 score. Example calculations are shown based on generated sample data

The Networked Nitrous Node: A Low-Power Field-Deployable COTS-based N2O gas sensor platform

We present a wireless nitrous oxide (N 2 O) gas sensor system consisting of a commercial high-current infrared N 2 O sensor wrapped in a “smart” sensor framework to make it suitable for battery-powered deployment. This framework consists of wireless mesh networking, data storage, additional environmental sensors, and a gas sensor power control circuit managed by a central microcontroller. The N 2 O sensor is the first order consumer of power and sampling N 2 O at approximately ten minute intervals yields an estimated system lifetime of 63 days when using four 18650 Li-ion batteries. The node stores data locally on SD card and wirelessly reports to a root PC that also stores data and displays to users in a simple graphical user interface. The system is composed of majority off-the-shelf components and any custom components were designed or programmed with open-source software. We expect these features will lead to this system being more easily understood, copied, and modified by engineers wishing to design similar sensor system frameworks and thereby allow even more power-prohibitive devices to be wirelessly deployed

A Brief Review of Speaker Recognition Technology

This paper reviews the development of speaker recognition systems from pre-computing days to current trends. Advances in various sciences which have allowed autonomous speaker recognition systems to become a practical means of identity authentication are also reviewed

Utilizing Sneak Paths for Memristor Test Time Improvement

Memristor technology is becoming an attractive option for memory architectures, in-memory computing, and logic applications due to their non-volatility, high density, and low power operation. However, these memristor-based devices are prone to defects because of the non-deterministic nature of nano-scale fabrication. This research describes a methodology for testing memristor circuits for fault detection and fault diagnosis using a unique property of memristor crossbar circuits – sneak paths. This research focuses on the stuck-at low resistance and stuck-at high resistance faults for our analysis. A 3 × 3 crossbar array was used as an example to demonstrate our fault dictionary-based diagnosis approach with improved test time. Our results show that fault diagnosis can be achieved only in three test vectors for the best case and a worst-case of m + 1 test vectors for an m × n array where m \u3e n

Fault Coverage Analysis Using Sneak Path Based Testing in Memristor Circuits

Testing memristor crossbar arrays is required to ensure high quality. However, inefficient testing can be prohibitively expensive. To evaluate the quality and efficiency of a test requires identifying the underlying relationship between fault coverage and test time as measured by faults detected per added test vector. This work describes a test methodology that utilizes sneak paths for efficient test generation. This work further describes the relationship between added test vectors and improved fault coverage for the efficient test generation methodology

A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures

This paper describes a CMOS-memristive Programmable Logic Device connected to CMOS XOR gates (mPLD-XOR) for realizing multi-output functions well-suited for two-level {NAND, AND, NOR, OR}-XOR based design. This structure is a generalized form of AND-XOR logic where any combination of NAND, AND, NOR, OR, and literals can replace the AND level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels of functions are implemented with novel programmable diode gates, which rely on the diode-like behavior of self-rectifying memristors, and the output levels of functions are realized with CMOS modulo-two counters. As an example, the circuit implementation of a 3-bit adder and a 3-bit multiplier are presented. The size and performance of the implemented circuits are estimated and compared with that of the equivalent circuits realized with stateful logic gates. Adding a feedback circuit to the mPLD-XOR allows the implementation of a multilevel XOR logic network with any combination of sums, products, XORs, and literals at the input of any XOR gate. The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding

Memristor Testing Needs Compared to Existing CMOS Testing Methods

This paper provides a comparison of established CMOS circuit testing concepts to the existing memristor testing efforts to identify memristor circuit testing needs. A very brief review of many CMOS testing concepts is provided to give a basis for comparison with memristor testing. A short simple overview of memristor theory precedes a survey of existing memristor testing efforts. Specifically, an analysis of testing sneak paths for fault detection and fault diagnosis is presented. A list of concepts that are equally applicable to both CMOS and memristor technologies have been described and those unique to memristor circuits have been identified